1. Field of the Disclosure
The present disclosure relates generally to a process and system of integrated circuit (IC) design optimization by automatically or manually creating design-specific cells with desired characteristics (such as, but not limited to performance, area, power, noise, etc.) that are implemented as standard cells from a set of post-layout patterns. A post-layout pattern represents a part or whole of a standard cell and contains information regarding the pattern including, but not limited to, layout, timing, area, power and noise.
2. Discussion of the Background Art
Incessant progress in IC manufacturing technologies is enabling the design of ever larger and complex circuits. The process of designing ICs can be broadly classified into two categories: custom and standard cell-based (see “Closing the Gap between ASIC & Custom,” David Chinnery, Kurt Keutzer; Kluwer Academic Publishers, ISBN 1-4020-7113-2, 2002, which is incorporated herein by reference in its entirety (hereinafter referred to as Chinnery book). In custom design, ICs are constructed at the transistor-level. These transistors are customized specifically for that design, and are often designed manually. For this reason, custom design process is labor-intensive, time consuming and expensive. Standard cell-based design, on the other hand, constructs ICs utilizing a library of small, generic, and predefined, fixed, set of building blocks called standard cells. As such, resultant quality (area, speed, power, etc) of such designs is limited and inferior to that of custom-designed ICs. In addition, the fixed (static) set of standard cells in a library is not amenable to the customization of an IC.
FIG. 1 shows the typical design flow in the standard cell-based methodology. The flow goes through the steps of logic synthesis (105) and technology mapping (110) to produce a design netlist (mapped to the standard cells existing in the fixed library (100)) from RTL. The mapped design netlist is then placed and routed to produce the final layout. Physical-aware logic optimization (115) is also performed to take advantage of accurate placement and routing information, thus resulting in faster convergence to design goals. The logic synthesis (optimization) and place-and-route steps are often necessary to be repeated (in an iterative fashion) until the desired characteristics of the design are achieved. In the entire design process the contents of the library (100) remain unchanged, which often leads to designs with inferior quality and contribute to longer design cycle.
Prior approaches at bridging the gap between custom designs and standard cell-based designs, can be broadly categorized under two groups—fixed library techniques (that do not change the standard cells in the library) and dynamic library techniques (that change the standard cells in the library).
Several fixed-library techniques have been proposed earlier (see Chinnery book, ICCD'1997, Page 110-115, “Discrete Drive Selection for Continuous Sizing,” R. Haddad, Van Ginneken Lukas P. P. P., N. Shenoy and U.S. Pat. No. 6,496,965, “Automated design of parallel drive standard cells,” Van Ginneken Lukas P. P. P., Nijssen; Raymond X. T., Buch; Premal., which are incorporated herein by reference in their entirety). These techniques typically rely on design-level analysis, optimization and abstraction. Techniques in this group include micro-architecture tuning (enabling more customized RTL design implementation, see Chapter: Improving Performance through Microarchitecture in Chinnery book), customized placement and floor-planning (enabling more customized physical design implementation, see Chapter: Physical Prototyping Plans for High Performance in Chinnery book) clock-skew techniques (enabling more customized clock-tree implementation, see Chapter: Useful-Skew Clock Synthesis Boosts ASIC Performance in Chinnery book), controlling process margins (enabling lesser loss in process variations, see Chapter: Controlling Uncertainty in High Frequency Designs), which are incorporated herein by reference in their entirety), parallel-drivers (enabling more customized use of drivers cells, see references: ICCD'1997, Page 110-115, “Discrete Drive Selection for Continuous Sizing,” R. Haddad, Van Ginneken Lukas P. P. P., N. Shenoy and U.S. Pat. No. 6,496,965, “Automated design of parallel drive standard cells,” Van Ginneken Lukas P. P. P., Nijssen; Raymond X. T., Buch; Premal), etc. Prior techniques using dynamic libraries create on-the-fly, design-specific, optimized transistor-level functional blocks directly from the functional specification. The functional specification of the netlist is represented as a Binary Decision Diagram (BDD), Zero-suppressed Decision Diagram (ZDD), other variants of decision diagrams, factored-form Boolean expression, etc. These abstract representations form the basis for creating context-specific standard cells (see U.S. Pat. No. 7,003,738, “Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process,” Bhattacharya; Debashis, Boppana; Vamsi, Murgai; Rajeev, Roy; Rabindra, and “Transistor-Level Optimization of Digital Designs with Flex Cells,” Rob Roy; Debashis Bhattacharya; Vamsi Boppana; IEEE Computer; February 2005 (Vol. 38, No. 2) pp. 53-61, which are incorporated herein by reference in their entirety)), as shown in FIG. 2. In this method, an abstract representation of the functional specification of a sub-section of design is mapped (210) to an interconnection of transistors, or transistor network. These mapping methods rely on metrics such as, number of transistors, stack depth, number of nets, number of terminals connected to nets, etc., to estimate layout characteristics such as transistor folds, diffusion area, wiring, parasitics, etc. The electrical and physical characteristics of the design-specific cell are then calculated based on these estimated parameters (215). In deep sub-micron processes, these metrics, however, are often incapable of accurately predicting the layout characteristics that strongly determine the final quality (e.g., performance, area, power, noise, etc.) of the design-specific cell. As a result, characterization (225) of the cell based on estimated layout parameters may be inaccurate. In a nutshell, the limitation of this method lies in the fact that any decisions made prior to complete cell layout (230) may result in unnecessary transistor-level optimization iterations before the cell is accepted for use in the standard cell-based flow.
Cell layout synthesis (230) is a computationally intensive task and it may often be impractical to embed that process in the creation of on-the-fly design-specific standard cells. On the other hand, without fully realizing and implementing the design-specific custom cells it is not possible to precisely converge on a design goal. This difficulty coupled with the reliance on estimated layout characteristics results in an open-loop methodology (shown by dotted lines in FIG. 2) that is incapable of addressing the creation of design-specific standard cells in advanced deep sub-micron processes.
In contrast, the present disclosure discloses a closed-loop dynamic library transformation.
Inaccuracies that are typically associated with design-level abstraction and analysis are addressed in the method of the present disclosure by the standard cell encapsulation of the created metacell. Key advantages of the present disclosure include, but are not limited to:                The automatic scheme of the present disclosure can create arbitrary structures from the cache patterns.        Accurate circuit simulation (rather than static timing analysis) is employed to characterize metacells.        The constituent cache patterns of a metacell are an integral part of the metacell (and hence are immune to disruptive influences of design-level placement and routing) and hence afford greater control during design optimization.        After characterization and view generation metacells are used as standard cells in design optimization.        
In contrast to “layout” related work described in the literature (see U.S. Pat. No. 5,764,533, “Apparatus and methods for generating cell layouts,” deDood; Paul C., which is incorporated herein by reference in its entirety), which primarily focuses on creation of standard cell layout from scratch, the method of the present disclosure creates and/or reuses existing layout patterns to create new layouts in order to meet various design constraints.
The present disclosure also provides many additional advantages, which shall become apparent as described below.